Technical Field
The present disclosure relates to the fabrication of FinFET transistors built on a substrate having a buried oxide layer and, in particular, to such devices in which a metal gate directly stresses the conduction channel.
Description of the Related Art
Integrated circuits typically incorporate FETs in which current flows through a semiconducting channel between a source and a drain, in response to a voltage applied to a gate. A traditional planar (2-D) transistor structure is shown and described below in greater detail. To provide better control of the current flow, FinFET transistors, sometimes called 3D transistors, have also been developed. A FinFET is an electronic switching device in which the planar semiconducting channel of a traditional FET is replaced by a semiconducting fin that extends outward, normal to the substrate surface. In such a device, the gate, which controls current flow in the fin, wraps around three sides of the fin so as to influence the current flow from three surfaces instead of one. The improved control achieved with a FinFET design results in faster switching performance and reduced current leakage. Intel described this type of transistor in an announcement on May 4, 2011, calling it by various names including a 3D transistor, a 3-D Tri-Gate transistor, or a FinFET. (See, for example, the article titled “How Intel's 3D tech redefines the transistor” located on the internet at http://news.cnetcom/8301-13924_3-20059431-64.html; see also U.S. Publication No. 2009/0090976 to Kavalieros et al., published on Apr. 9, 2009; U.S. Pat. No. 8,120,073 to Rakshit et al.; U.S. Pat. No. 7,973,389 to Rios et al.; U.S. Pat. No. 7,456,476 to Hareland et al.; and U.S. Pat. No. 7,427,794 to Chau et al.).
Separately from the emergence of FinFETs, strained silicon transistors were developed to increase the mobility of charge carriers, i.e., electrons or holes, in the semiconducting channel. Introducing compressive stress into a PFET transistor tends to increase hole mobility in the channel, resulting in a faster switching response to changes in voltage applied to the gate. Likewise, introducing tensile stress into an NFET transistor tends to increase electron mobility in the channel, also resulting in a faster switching response.
Many methods have been developed by which tensile or compressive stress can be introduced into planar transistors. One way is by replacing bulk silicon in the source and drain regions, or in the channel itself, with epitaxially grown silicon compounds such as silicon germanium (SiGe), for example. The term epitaxy refers to a controlled process of crystal growth in which a new, epitaxial, layer of a crystal is grown from the surface of a bulk crystal, while maintaining the same crystal structure of the underlying bulk crystal. Another way to introduce stress is by introducing new channel materials such as III-V semiconductors. It has also been shown that cryogenic implantation of phosphorous atoms into the silicon is another way to increase mobility in the channel. Whereas, at room temperature, implantation causes crystal defects such as dislocations and stacking faults that must be annealed, such defects are not observed at temperatures below −60 C. Alternatively, stress can be induced from below the device by using various types of SOI substrates. Another technique that has produced high performance devices causes stress by incorporating one or more stress liners on top of the gate. (H. S. Yang et al., International Electron Devices Meeting (IEDM) Technical Digest, 2004, p. 1075).
Some methods of introducing stress have been investigated for use with FinFET structures. Process technologies that have been developed to fabricate FinFETs having strained channels generally have employed a replacement metal gate (RMG) process that is well known in the art. The RMG technique entails forming the fin, then putting in place a sacrificial gate, then forming the source, and drain, after which the sacrificial gate is removed and replaced with a permanent metal gate. RMG is an alternative to the conventional “metal gate first” process sequence in which the gate is formed first, and is then used as a mask for implanting source and drain regions so that the source and drain are automatically self-aligned to the gate.